■ 제품필수정보

제조사	Nexperia
제조사품명	74AUP2G08DC,125
간략설명	Nexperia 74AUP2G08DC,125, Dual 2-Input ANDSchmitt Trigger Logic Gate, 8-Pin VSSOP

■ 제품사양

Logic Function = AND
장착형태 = Surface Mount Number of Elements = 2 Number of Inputs per Gate = 2 Schmitt Trigger Input = Yes
패키지 = VSSOP
핀수 = 8 Logic Family = AUP Input
타입 = CMOS Maximum Operating Supply Voltage = 3.6 V Maximum High Level Output Current = -4mA Maximum Propagation Delay Time @ Maximum CL = 24 @ 30 pF Minimum Operating Supply Voltage = 0.8 V Maximum Low Level Output Current = 4mA Propagation Delay Test Condition = 30pF Low-power dual 2-input AND gate, The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Low static power consumption, ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial power-down mode operation Multiple package options